In designing and fabricating programmable integrated circuits, PLD integrated circuits including, for example, CPLD or FPGA devices, are frequently used. A circuit designer typically approaches the design of a device using FPGA or CPLD technology by accessing a library of known functions, which are selected as circuit elements, and which are then coupled together using design tools to form useful circuitry. The output of the design process is typically a netlist of wired connections, or other connectivity information, coupling instances of the selected circuit elements. Circuit elements in such libraries include relatively low level devices such as input and output buffers, clock buffers, NAND and NOR gates. Circuit elements may further include higher level devices such as registers, flip-flops, register files, memory arrays, and even processors or CPUs, and specialized functions such as digital signal processors (DSPs) may be provided as library elements.
By selecting the necessary circuit elements and coupling them together, a circuit designer can quickly create a new functional integrated circuit. Because CPLD/FPGA technology allows automated tools to program a pre-existing completed packaged integrated circuit device, the integrated circuit can quickly be completed as a physical device and tested. In contrast, the manufacture of custom, semi-custom or application specific integrated circuits (ASICs) requires that the circuit designer complete the design and then wait for silicon devices to be manufactured, packaged, tested and delivered as integrated circuits before the physical devices are available. Thus, PLD technology allows fast design, verification and production of integrated circuits. Further, certain FPGA devices are programmed using non-volatile memory devices or even one time programmable elements to contain the programming, e.g. the interconnect selections and the circuit functional selections. Since in some cases these devices can be reprogrammed, changes to the design or modifications to fix errors in the design may be made quickly and without the need for waiting for additional silicon manufacture to occur.
Like many integrated circuits, present FPGA and CPLD designs use more power than is desirable. Power consumed may be described as static and dynamic power. Dynamic power is consumed during circuit operations when one or more elements of the circuit are changing state. One approach to saving dynamic power in current PLD integrated circuits, such as FPGAs or CPLDs, which are typically CMOS logic devices, is to provide clock enables to the clocked elements including registers or flip-flops. When the clock to a clocked element is disabled by an enable signal, the register or flip-flop transistors coupled to the clock line will not change state, thus saving dynamic power. When a particular circuit element that is clocked is not in use, the circuit can selectively disable the clock to that portion, and thereby save power that would otherwise be consumed with each clock transition.
However, the use of many of these clock enable lines in a PLD design places a high demand on the routing area resources of the device. The clock enable line is an additional signal, in addition to the clock signal, that is now routed to many clocked elements on the programmed integrated circuit. In some prior art FPGAs, the clock enable lines are even routed to some circuits where they are never used. The clock enable lines therefore take up valuable routing circuit area, limiting the availability of routing area for other purposes.
In the prior art, clock gating circuits are known for providing a clock signal that is gated by an enable signal. Because a change in the enable signal could appear in the gated clock signal as a partial or “runt” output clock signal if a simple logic gate were used, clock gating circuits are designed to prevent erroneous outputs on the gated clock signal.
FIG. 1 depicts, for example, a first clock gating circuit of the prior art described in U.S. Pat. No. 6,456,115, which is hereby incorporated herein by reference. The patent provides several similar embodiments for providing a gated clock signal without requiring a flip flop or latch to do so. In FIG. 1, circuit 10 includes elements 11 and 13 which receive both the clock and inverted clock signals CK and CK_, and pass the output of the element to the next element only when the clock CK falls. The ENABLE signal and the clock signal CK_ are then combined at the logic gate 17 to form the output GATED CLOCK. The use of the circuit of FIG. 1 provides clock output GATED CLOCK that is gated by the input ENABLE signal without forming “runt” clock pulses on the output. The reference patent provides several other embodiments of the circuit of FIG. 1 using, for example, NOR gates instead of NAND gates, and other modifications that provide a gated clock output signal.
FIG. 2 depicts an alternative prior art approach gated clock circuit 20 that uses a register 23 to synchronize the enable signal ENABLE to the free running input clock signal CK. The output of the register Q and the clock CK are then logically combined by a logic gate 21 which then outputs the signal GATED CLOCK. This circuit is described in U.S. Pat. No. 6,782,486, which is also hereby incorporated by reference herein.
A common feature of certain integrated circuit logic devices is the use of multiple clocks that are multiplexed to form a selected clock for a particular section. For example, in FIG. 3, using the S0-S1 inputs to clock multiplexer 35, the selection is made between a locally generated clock LGCK, a system clock CK which may be free running or operate at a different frequency, and a fixed value—that is, no clock at all. The multiplexer output is then buffered by output driver 33 to provide a clock output signal OUTCLK with sufficient drive to supply a group of synchronous circuits as the load.
The use of a clock multiplexer to select clocks is also sometimes done in a manner to prevent the clock output signal provided by the multiplexer from making false or short pulse transitions; for example, when the multiplexer selection input changes. FIG. 4 depicts a known clock multiplexer circuit 40 for selection between two clock signals CK1 and CK2, which provides an output signal OUTCK. The input select signal SEL is synchronized to the current output clock signal by registers 51 and 53 and when the input SEL transitions from one selection value to the other, the circuit provides a robust transition to the newly selected clock at the output. This circuit is described in U.S. Pat. No. 5,315,181, which is hereby incorporated by reference herein.
The use of clock gating circuits to save dynamic power in synchronous circuitry used in PLDs such as CPLDs and FPGAs continues to increase. A continuing need thus exists for an improved gated clock distribution circuit, and methods for facilitating the use of clock gating to lower power consumption in these PLD devices without the disadvantages of the prior art circuits.